library ieee;
use ieee.std_logic_1164.all;

entity controllerBlocktb is
	
end entity controllerBlocktb;

architecture RTL of controllerBlocktb is

	component controllerBlock
	
	port (
		reset, start, setMultiplicand, setMultiplier, overFlow, clk: in bit;
		clr, regmulti, enCtr, shift, done : out bit;
		holdShift, enLoad, sumLoad : out bit
	);
		
	end component;
	
	for all : controllerBlock use entity work.controllerBlock(RTL);
	
	signal clkIn, startIn, setMultiplicandIn, setMultiplierIn, overFlowIn : bit := '0';
	signal resetIn: bit := '1';
	signal clrOut, regmultiOut, enCtrOut, shiftOut, doneOut, sumLoadOut : bit;
	
begin

	clkIn <= not clkIn after 10 ns;
	
	SHFT : controllerBlock port map (resetIn, startIn, setMultiplicandIn, setMultiplierIn, overFlowIn, clkIn, clrOut, regmultiOut, enCtrOut, shiftOut, doneOut);
	
	tb : PROCESS
		
	begin
	
	wait for 25 ns;
	
	resetIn <= '0';
	
	wait for 55 ns;
	
	startIn <= '1';
	
	wait for 85 ns;

	startIn <= '0';
	setMultiplicandIn <= '1';
	
	wait for 55 ns;	

	setMultiplicandIn <= '0';
	setMultiplierIn <= '1';
	
	wait for 55 ns;
	
	setMultiplierIn <= '0';
	
	
	--Check to see if the controller will swap between the En_ctr and Shift States
	wait for 55 ns;
	wait for 55 ns;
	wait for 55 ns;
	
	overFlowIn <= '1';
	
	wait for 55 ns;
	
	overFlowIn <= '0';
	
	wait for 55 ns;
	
	resetIn <= '1';
	
	
	--check to see if it will return to the clr ctate from the regmulti state
	wait for 55 ns;
	
	resetIn <= '0';
	
	wait for 55 ns;
	
	startIn <= '1';
	
	wait for 55 ns;
	
	resetIn <= '1';
	
	--check to see if it will change from the En_Ctr state to the clr state
	wait for 55 ns;
		
	resetIn <= '0';
	
	wait for 55 ns;
	
	startIn <= '1';
	
	wait for 55 ns;

	startIn <= '0';
	setMultiplicandIn <= '1';
	
	wait for 55 ns;	

	resetIn <= '1';
	
	--check to see if it will change from the shift state to the clr state
	wait for 55 ns;

	resetIn <= '0';
	
	wait for 55 ns;
	
	startIn <= '1';
	
	wait for 55 ns;

	startIn <= '0';
	setMultiplicandIn <= '1';
	
	wait for 55 ns;	

	setMultiplicandIn <= '0';
	setMultiplierIn <= '1';
	
	wait for 55 ns;
	
	setMultiplierIn <= '0';
	resetIn <= '1';
	
	wait;
		
	end PROCESS;
	

end architecture RTL;
